The present invention is directed to semiconductor devices and, more particularly, to a trench MOSFET with reduced Miller capacitance having improved switching speed characteristics.
The semiconductor industry is witnessing an increasing demand for low-output-voltage DCxe2x80x94DC converters with very fast transient response and higher power efficiency for high frequency power conversion applications. When the operation frequency reaches 1 MHz or even higher, the power losses of a synchronous buck DCxe2x80x94DC converter will be dominated by the switching losses. Switching losses in a power MOSFET occur during charging/discharging the drain-gate feedback capacitance. The corresponding gate charge is called Miller Charge. Thus, the reduction of Miller capacitance is one of most important focus to improve DCxe2x80x94DC converter efficiency.
Also, as the cell density and speed of a microprocessor increases, more current is needed to power the microprocessor. This means that the DCxe2x80x94DC converter is required to provide a higher output current. The increase of the output current raises the conduction loss of not only the lower switches but also the upper switches in synchronous DCxe2x80x94DC converter. Therefore, in order to power an advanced microprocessor, the power MOSFETS, which are used as the upper and the lower switches in a DCxe2x80x94DC converter must have both low switching power losses and low conduction power losses. The switching losses can be reduced by lowering on-resistance. Unfortunately, lowering the on-resistance raises the Miller capacitance. For example, in order to reduce the on-resistance of a power MOSFET, the most efficient way is to reduce the device cell pitch and increase the total channel width. Both of these result in an increase of the drain-gate overlay area. As the consequence, the device""s Miller capacitance, or Miller charge increases.
Due to gate to drain capacitance""s significant impact on device switching speed, a series of improvements for minimizing it""s impact have been proposed. These improvements include tailoring of source-drain ion implant angles and gate spacers, in order to obtain sufficient gate overlap of source-drains for maintaining low channel resistance, while still minimizing the associated capacitance values. One such effort to minimize Miller capacitance is a process step that locally increases the gate oxide thickness in the region of gate to drain overlap. However, that process is difficult to control because you need to maintain overlap while growing the thick oxide in the bottom of the trench and etching back. Therefore, what is needed is a method that will achieve low switching power losses and low conductivity power losses.
The present invention is directed towards a power device that has low switching power losses and low conductivity power losses. A power device having features of the present invention comprises a first substrate layer that is highly doped with a dopant of a first conductivity type, forming a drain. Over this first layer is a second layer that is lightly doped with the same conductivity dopant as the first layer. Above this second layer is a third layer, doped with a second conductivity dopant that is opposite in polarity to the first conductivity type. A fourth layer highly doped with the first conductivity dopant, is on the opposite surface of the semiconductor substrate. A trench extends from this fourth layer, into the second layer. This trench divides the fourth layer into a plurality of source regions. The trench also has sidewalls adjacent to the third and fourth layers for controlling a channel layer. Finally, this trench also has upper and lower conductive layers that are separated by a dielectric layer.
According to another aspect of the invention, the upper conductive layer in the trench forms a gate electrode for controlling current through a channel adjacent the sidewall of the trench. The polysilicon gate layer, the polysilicon shield layer and the interlevel dielectric layer are suitably sized so that the bottom of the polysilicon gate layer is proximate the curvature of the well region. This will minimize the overlap between the gate and drain, and therefore minimize the gate-to-drain capacitance.
According to still another aspect of the invention, the device originally described can have a source metal layer over the device and in electrical contact with the fourth layer, so that it is in contact with the source regions. This source metal also is in contact with the third layer doped with the second conductivity type. This metal layer will also be in contact with the lower conductive layer of the trench at peripheral locations around the cells of the device. The lower conductive layer, or shield layer, will be at the same electrostatic potential as the source. Now the capacitance at the bottom of the trench is no longer gate-to-drain it is now gate-to-source, because the shield is tied to the source.